TEAM LEAD

​Selected Publications
(Updated on June 30th, 2017, from dblp)
​
[J] Shouyi Yin, Jiangyuan Gu, Dajiang Liu, Leibo Liu, Shaojun Wei: Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on Dual-Vdd CGRAs. IEEE Trans. on CAD of Integrated Circuits and Systems 35(9): 1475-1488 (2016)
[J] Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei: A Fast and Power-Efficient Memory-Centric Architecture for Affine Computation. IEEE Trans. on Circuits and Systems 63-II(7): 668-672 (2016)
[J] Shouyi Yin, Xinhan Lin, Leibo Liu, Shaojun Wei: Exploiting Parallelism of Imperfect Nested Loops on Coarse-Grained Reconfigurable Architectures. IEEE Trans. Parallel Distrib. Syst. 27(11): 3199-3213 (2016)
[J] Shouyi Yin, Dajiang Liu, Yu Peng, Leibo Liu, Shaojun Wei: Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures. IEEE Trans. VLSI Syst. 24(2): 507-520 (2016)
[J] Shouyi Yin, Peng Ouyang, Tianbao Chen, Leibo Liu, Shaojun Wei: A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing. IEEE Trans. VLSI Syst. 24(4): 1305-1318 (2016)
[J] Shouyi Yin, Xianqing Yao, Dajiang Liu, Leibo Liu, Shaojun Wei: Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures. IEEE Trans. VLSI Syst. 24(5): 1895-1908 (2016)
[J] Shouyi Yin, Pengcheng Zhou, Leibo Liu, Shaojun Wei: Trigger-Centric Loop Mapping on CGRAs. IEEE Trans. VLSI Syst. 24(5): 1998-2002 (2016)
[J] Shouyi Yin, Weizhi Xu, Jiakun Li, Leibo Liu, Shaojun Wei: CWFP: Novel Collective Writeback and Fill Policy for Last-Level DRAM Cache. IEEE Trans. VLSI Syst. 24(7): 2548-2561 (2016)
[C] Shouyi Yin, Zhicong Xie, Chenyue Meng, Leibo Liu, Shaojun Wei: Multibank memory optimization for parallel data access in multiple data arrays. ICCAD 2016: 32
[C] Shouyi Yin, Xianqing Yao, Tianyi Lu, Leibo Liu, Shaojun Wei: Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory. ICCAD 2016: 127
[J] Peng Ouyang, Shouyi Yin, Chunxiao Xing, Leibo Liu, Shaojun Wei: Energy management on DVS based coarse-grained reconfigurable platform. NANOARCH 2016: 49-54
[J] Shouyi Yin, Peng Ouyang, Leibo Liu, Yike Guo, Shaojun Wei: Fast Traffic Sign Recognition with a Rotation Invariant Binary Pattern Based Feature. Sensors 15(1): 2161-2180 (2015)
[J] Shouyi Yin, Hao Dong, Guangli Jiang, Leibo Liu, Shaojun Wei: A Novel 2D-to-3D Video Conversion Method Using Time-Coherent Depth Maps. Sensors 15(7): 15246-15264 (2015)
[J] Peng Ouyang, Shouyi Yin, Yuchi Zhang, Leibo Liu, Shaojun Wei: A Fast Integral Image Computing Hardware Architecture With High Power and Area Efficiency. IEEE Trans. on Circuits and Systems 62-II(1): 75-79 (2015)
[J] Dajiang Liu, Shouyi Yin, Yu Peng, Leibo Liu, Shaojun Wei: Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures. IEEE Trans. VLSI Syst. 23(11): 2581-2594 (2015)
[J] Peng Ouyang, Shouyi Yin, Leibo Liu, Shaojun Wei: Energy Management on Battery-Powered Coarse-Grained Reconfigurable Platforms. IEEE Trans. VLSI Syst. 23(12): 3085-3098 (2015)
[C] Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei: A 83fps 1080P resolution 354 mW silicon implementation for computing the improved robust feature in affine space. CICC 2015: 1-4
[C] Chenyue Meng, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei: Efficient memory partitioning for parallel data access in multidimensional arrays. DAC 2015: 160:1-160:6
[C] Shouyi Yin, Dajiang Liu, Leibo Liu, Shaojun Wei, Yike Guo: Joint affine transformation and loop pipelining for mapping nested loop on CGRAs. DATE 2015: 115-120
[C] Shouyi Yin, Jiakun Li, Leibo Liu, Shaojun Wei, Yike Guo: Cooperatively managing dynamic writeback and insertion policies in a last-level DRAM cache. DATE 2015: 187-192
[C] Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei: RNA: a reconfigurable architecture for hardware neural acceleration. DATE 2015: 695-700
[C] Shouyi Yin, Pengcheng Zhou, Leibo Liu, Shaojun Wei: Acceleration of Nested Conditionals on CGRAs via Trigger Scheme. ICCAD 2015: 597-604
[C] Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei: Neural approximating architecture targeting multiple application domains. ISCAS 2015: 2509-2512
[C] Xu Dai, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei: A Multi-modal 2D + 3D Face Recognition Method with a Novel Local Feature Descriptor. WACV 2015: 657-662
[J] Ruoyu Xu, Wai Chiu Ng, George Jie Yuan, Shouyi Yin, Shaojun Wei: A 1/2.5 inch VGA 400 fps CMOS Image Sensor With High Sensitivity for Machine Vision. J. Solid-State Circuits 49(10): 2342-2351 (2014)
[J] Shouyi Yin, Xu Dai, Peng Ouyang, Leibo Liu, Shaojun Wei: A Multi-Modal Face Recognition Method Using Complete Local Derivative Patterns and Depth Maps. Sensors 14(10): 19561-19581 (2014)
[C] Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei: Extending lifetime of battery-powered coarse-grained reconfigurable computing platforms. DATE 2014: 1-6
[C] Dajiang Liu, Shouyi Yin, Leibo Liu, Shaojun Wei: Exploiting Outer Loop Parallelism of Nested Loop on Coarse-Grained Reconfigurable Architectures. FCCM 2014: 32
[C] Dajiang Liu, Shouyi Yin, Leibo Liu, Shaojun Wei: Polyhedral model based mapping optimization of loop nests for CGRAs. DAC 2013: 19:1-19:8